August

S.NOTITLE & AUTHORSPAGE NO
1Intelligent Vehicle Monitoring System using Wireless Communication
Authors: Dontha Supriya, Mrs. Mythili Devi, Mr. SK Saidulu, Prof B Kedarnath
1-3
2Implementation of Wireless Sensor Networks for Long Range
Authors: J Julinesther Kanagaroja, Mr. R. Mallikarjun, Dr. M. Narendra Kumar, Prof B Kedarnath
4-8
3Development of a Cell Phone Based Vehicle Remote Control System
Authors: Koppula Srilatha, Mr. SK Saidulu, Mr. M Suman Kumar, Prof B Kedarnath
9-12
4Position Matching Based Autonomous Speed Regulation System for Vehicles
Authors: Kummari Sirisha, Mr. R. Mallikarjun, Mr. SK Saidulu, Prof B Kedarnath
13-15
5Design and Implementation of Real Time Embedded Tele-Health Monitoring System
Authors: M Balaraju, Mr. Jeevan, Dr. M. Narendra Kumar, Prof B Kedarnath
16-19
6Development on Gas Leak Detection & Location System Based On Wireless Sensor Network
Authors: Merugu Sreelatha, Mrs. J. L Divya Shivani, Mr. SK Saidulu, Prof B Kedarnath
20-23
7Design of Dedicated Reversible Quantum Circuitry for Square Computation
Authors: Akutota Vinay Kumar, Mrs.A Swetha, Mr. M Suman Kumar, Prof B Kedarnath
24-29
8Mach-Zehnder Interferometer based All Optical Reversible Carry-Look ahead Adder
Authors: Allada Shiva Kumar, Mrs. N Laxmi, Mrs. S Vasanti, Prof B Kedarnath
30-35
9Area-Delay-Power Efficient Carry Select Adder
Authors: Gaddam Rekha, Mrs. S Vasanti, Mrs. A Swetha, Prof B Kedarnath
36-38
10Parallel Multiplier Accumulator Based on Radix-2 Modified Booth Algorithm by Using VLSI Architecture
Authors: Gade Sreedhar Reddy, Mr. N Srinivas, Mr. M Suman Kumar, Prof B Kedarnath
39-42
11Design and Estimation of Delay, Power and Area for Parallel Prefix Adders
Authors: Madagani Nagamani, Mr. Sharath Chandra, Mrs. Premlatha, Prof B Kedarnath
43-49
12Energy Efficient Code Converters Using Reversible Logic Gates
Authors: Thonta Ashwini, Mrs. Premlatha, Mrs. N Laxmi, Prof B Kedarnath
50-53
13High Performance and Power Efficient 32-bit Carry Select Adder using Hybrid PTL/CMOS Logic Style
Authors: L N Krishna, Ms. S Swapna, Mrs. N Laxmi, Dr. M. Narendra Kumar
54-55
14FPGA Implementation of Low Logical Cost Conservative Reversible Adders using Novel PCTG
Authors: Tazeen Naz Tabassum, Mr. SK Saidulu, Mrs. Mythili Devi, Prof B Kedarnath
56-61
15University Development Zones for India
Author: Dr. Krishnendu Sarkar
62-65
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